Advances in microprocessor and other technologies have greatly increased the speeds at which computers can operate, and faster computer processors require faster memories to take advantage of the increased speed. In order to increase memory speed, some memories employ an echo clock or data strobe which follows an input clock signal to speed the reading of data from memory. The echo clock signal speeds the reading of data from the data output lines of a memory circuit by allowing a microprocessor, or other external circuit, to read the data from the output lines as soon as it is valid, instead of waiting a specified period of time.
Because echo clocks are relied upon by a processor or other external circuitry to indicate valid data, one must ensure that the echo clock does not prematurely indicate valid data. Conversely, if the echo clock is delayed for too long a period of time in order to ensure that the data is valid, a less than optimal increase in data retrieval speed will be realized. Therefore, it is essential to match the echo clock as closely as possible to the memory input clock, which triggers the release of data from the memory circuit.
One method of matching an echo clock to the memory input clock involves the use of phase locked loop (PLL) circuits. PLLs are used to generate an echo clock that is synchronized with the memory input clock. However, since PLLs are designed to operate at specific frequencies, echo clocks generated by PLLs are able to lock the echo clock with the input clock only for a particular frequency range. Additionally, given the very tight timing tolerances used in today's processors and memory devices, it can be difficult to match a PLL generated echo clock to the precise time at which valid data is available at each and every memory buffer. That is to say, although a PLL generated echo clock may closely match the time at which valid data is available from a particular memory buffer, the echo clock may not so closely match the time at which valid data is available at other memory buffers. In addition, PLLs are relatively complicated circuits, and can be costly to design and manufacture.